• 专利附录
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    • 专利摘要:
    The invention relates to a 3D stack comprising: - a first chip having first interconnect pads of rectangular section, the first interconnect pads having a first pitch of repetition in a first direction and a second pitch of repetition in a second direction perpendicular to the first direction; a second chip having second interconnection pads, the second interconnection pads having a third pitch of repetition in the first direction and a fourth pitch of repetition in the second direction, at least a portion of the second interconnect pads being in contact with the first interconnect pads for electrically coupling the first and second chips; and wherein: the first interconnect pads have a first dimension in the first direction equal to m times the third pitch of repetition and a second dimension in the second direction equal to n times the fourth pitch of repetition; the first interconnection pads are separated two by two in the first direction by a first distance equal to q times the third repetition pitch; the first interconnection pads belonging to each other are separated two by two in the second direction by a second distance equal to r times the fourth repetition step, where m, n, q and r are non-zero natural integers; the second interconnection pads are interconnected in a plurality of groups, each group comprising a number N of second interconnected interconnection pads such that: N = (m + q) (n + r), each group being electrically connected to a first interconnection pad by at least one of the second interconnect pads of the group.
    公开号:FR3078823A1
    申请号:FR1852110
    申请日:2018-03-12
    公开日:2019-09-13
    发明作者:Didier Lattard
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    The present invention relates to three-dimensional integrated circuits (3D IC) and relates more particularly to a 3D stack of electronic chips which tolerates a significant misalignment between two superimposed electronic chips.
    STATE OF THE ART
    Three-dimensional (3D) integration consists of stacking several electronic chips (also called integrated circuits) and connecting them electrically, for example by a bonding technique. This approach notably makes it possible to reduce the bulk of so-called “heterogeneous” systems which are composed of circuits belonging to different technologies, for example an image sensor comprising a matrix of photodiodes and a CMOS image processing circuit comprising transistors . 3D integration also increases the density of transistors per unit area without reducing their dimensions and reduces the power consumption of a system, replacing long horizontal interconnections with short vertical interconnections.
    A 3D circuit can adopt several architectures depending in particular on how the chips are stacked, the orientation of the chips and the type of bonding.
    Stacking can be carried out according to different approaches: from plate to plate (for “wafer-to-wafer” in English), from chip to plate (“die-to-wafer”) or even from chip to chip (“die- to-die ”). The plate-to-plate stacking technique is the fastest in number of chips bonded per hour, since it is a collective bonding at the scale of the silicon plates. It is also the most precise for a given bonding speed. On the other hand, unlike the other two techniques, it does not offer the possibility of assembling only the functional chips (called "Know Good Dies"), selected after a series of tests and the cutting of the plates. The yield after assembly obtained by the plate-to-plate technique is therefore lower than the yield of the chip-to-plate technique and the yield of the chip-to-chip technique. This last technique is naturally the longest to implement, because the chips are glued together two by two after cutting the plates.
    When the chips (or plates) are oriented in the same direction, the front side of a chip is glued to the back side of another chip. This method of assembly is called "back-to-face". Conversely, when the chips (or the plates) are assembled after turning one of them over, the chips are glued front face against front face ("face-to-face") or rear face against rear face ("backto -back ”).
    FIG. 1 illustrates an example of a 3D circuit integrating a first chip 100a and a second 100b in a box (here BGA) composed of a substrate 110 and a cover 120. The first chip 100a, called the upper chip, is stacked on the second chip 100b, called the lower chip. Each chip comprises, from the rear face BS to the front face FS, a silicon substrate 101, a first functional block 102 (or set of technological levels) called FEOL (“Front End Of Line”) which groups together the active components (eg . transistors) of the chip, and a second functional block 103 called BEOL ("Back End Of Line") which groups together the passive components (eg resistors, inductors, capacitors) and the interconnections of the chip. The interconnections of the BEOL 103 block are typically distributed in several metal levels.
    The chips 100a-100b are in this example assembled front face against front face (“face-to-face”) by a direct bonding technique of the hybrid type. Each chip has on the front face FS a bonding surface composed of interconnection pads 104 of metal and of insulating portions 105, typically of silicon oxide. The insulating portions 105 separate the interconnection pads 104. The interconnection pads 104 of the first chip 100a are in direct contact with the interconnection pads 104 of the second chip 100b, so as to electrically couple the two chips 100a 100b. Interconnection pads, typically made of copper, help bond the two chips and route electrical signals from one chip to another. The interconnection pads 104 on the front face FS of each chip are generally organized in rows and columns, in the form of a matrix or mesh. The set of interconnection pads 104 belonging to the two chips 100a100b constitutes a so-called 3D interconnection structure.
    Through vias 106 designated by the acronym TSV from the English "Through Silicon Via" further extend through the lower chip 100b, and more particularly from the first metal level of the BEOL block to the rear face BS. These through vias 106 are used to route the electrical signals from the front face FS of the chip 100b to its rear face BS. The substrate 101 of the lower chip 100b is specially thinned to allow the realization of these vias.
    The signals are then distributed (or redistributed) on the rear face BS of the lower chip 100b, using a redistribution layer 107 called RDL ("redistribution layer"). The role of this RDL 107 layer is to electrically connect each of the TSV 106 to a contact recovery area, from which the signals are routed to the outside of the housing protecting the chips.
    A known assembly technique consists in adopting the same geometry for the matrix of interconnection pads 104 of the first chip 100a and the matrix of interconnection pads 104 of the second chip 100b. The interconnection pads 104 of the chips 100a-100b are then of the same shape, for example of square section (in the plane of the front face FS), of the same dimensions and spaced apart by the same distance. With such a 3D interconnection structure, the slightest misalignment when bonding the two chips results in a reduction in the contact surface between the interconnection pads 104. However, a reduction in the contact surface is detrimental for the quality of bonding, in particular from a mechanical point of view, and for the electrical performance of the stack. As the misalignment tends to vary from one stack of chips to another (even when the lower / upper chips belong to the same plate, ie chip-to-plate or plate-to-plate approach), a dispersion linked to the misalignment appears in the 3D circuit performance.
    The document [“Ultra-fine Pitch 3D Integration Using Face-to-Face Hybrid Wafer Bonding Combined with a Via-Middle Through-Silicon-Via Process”, SW. Kim et al., Electronic Components and Technology Conference (ECTC), IEEE 66th, 2016] offers a solution to guarantee a constant contact surface between the 3D interconnection pads of two chips stacked on top of each other. This solution, illustrated by FIG. 2, consists in adopting matrices of interconnection pads of different geometries. The upper chip 100a comprises a plurality of interconnection pads 104a of square section arranged in rows and columns, with a repetition pitch (“pitch” in English) identical in the two directions, for example equal to 3.6 μm. The interconnection pads 104a then measure 0.9 μm on the side, ie% of the repetition step. The lower chip 100b comprises interconnection pads 104b also arranged in a square mesh whose repetition pitch is equal to 3.6 μm. The interconnection pads 104b however measure 2.7 pm on a side, or 3 soit of the repetition step.
    In the case shown in FIG. 2, that of perfect alignment between the two chips, each interconnection pad 104a of the upper chip 100a is positioned in the center of an interconnection pad 104b of the lower chip 100b. The contact surface between the pads 104a-104b is equal to the area of the smallest pad, 104a. As long as the pad 104a does not exceed the perimeter of the pad 104b, that is to say as long as the misalignment between the two chips does not exceed 0.9 µm in the direction of the lines and / or in the direction of the columns , this contact surface is also constant. As indicated in the document, a constant contact resistance limits the dispersion of electrical performance within the same 3D circuit and between several 3D circuits, in particular in terms of electrical resistance.
    Patent application US2017 / 154873 describes another stack of electronic chips which tolerates significant misalignment and guarantees a constant contact surface within a certain tolerance range. The 3D interconnection pads are in this stack located on the periphery of the chips.
    Figure 3 is a sectional view of the stack taken at the bonding interface and limited to two 3D interconnection pads belonging to different chips. The interconnection pad 104a of the upper chip and the interconnection pad 104b of the lower chip have rectangular sections of the same dimensions and are oriented perpendicularly to each other. The ratio length L to width W of the pads 104a-104b is between 2 and 4. The maximum tolerated misalignment, allowing a constant contact surface to be obtained, is in each direction equal to ± L / 2, ie a tolerance interval of length L.
    The 3D interconnection structures described above make the performance of 3D circuits more homogeneous and improve their reliability, but complicates manufacturing, in particular the planarization stage of the bonding surfaces by chemical mechanical planarization (CMP). ). Indeed, the metal (copper) which constitutes the interconnection pads is not distributed uniformly on the surface of the chips. In the solution proposed by SW. Kim et al., The density of metal, which represents the surface of the studs on the total bonding surface, is only about 6% (0.9 2 / 3.6 2 ) for the lower chip. Large portions of silicon oxide therefore separate the interconnection pads 104b (cf. FIG. 2). The oxide portions are also very large on the surface of the chips of document US2017 / 154873, because of the perpendicular orientation of the studs and their position at the periphery of the chips. As silicon oxide is polished faster than metal, it is difficult to obtain a planar bonding surface with such structures.
    SUMMARY OF THE INVENTION
    There is therefore a need to provide a stack of electronic chips which is tolerant to misalignment, reliable, easy to produce and whose electrical performance is identical whatever the value of the misalignment within a tolerance interval.
    According to the invention, there is a tendency to satisfy this need by providing a 3D stack of electronic chips comprising:
    - A first chip having on a first face a plurality of first interconnection pads of rectangular section, arranged in rows and columns, the columns of first interconnection pads having a first repeating step in a first direction and the lines of first interconnection pads having a second repetition step in a second direction perpendicular to the first direction;
    a second chip having, on a second face glued to the first face of the first chip, a plurality of second interconnection pads arranged in rows and in columns, the columns of second interconnection pads having a third repetition step in the first direction and the lines of second interconnection pads having a fourth repetition step in the second direction, at least part of the second interconnection pads being in contact with the first interconnection pads to electrically couple the first and second fleas ;
    and in which:
    - the first interconnection pads have a first dimension in the first direction equal to m times the third repetition step, where m is a non-zero natural integer, and a second dimension in the second direction equal to n times the fourth repetition step , where is a non-zero natural integer;
    - the first interconnection pads belonging to the same row and to two consecutive columns are separated in the first direction by a first distance equal to g times the third repetition step, where g is a non-zero natural integer;
    - the first interconnection pads belonging to the same column and to two consecutive lines are separated in the second direction by a second distance equal to r times the fourth repetition step, where a non-zero natural integer remains;
    - the second interconnection pads are interconnected in a plurality of groups, each group comprising a number N of second interconnected interconnection pads such as:
    N = (m + g) (n + r), each group being electrically connected to a first interconnection pad by at least one of the second interconnection pads of the group.
    For each of the first interconnection pads belonging to the first chip, there is provided a group of N (N being necessarily greater than or equal to 4) second interconnection pads regularly distributed on the surface of the second chip and electrically interconnected. By thus multiplying the number of second pads associated with each first pad, a better density of metal can be obtained on the surface of the second chip. The preparation of the second chip before it is bonded, and in particular the planarization step of its bonding surface, is thereby facilitated.
    The arrangement of the first studs and the second studs, in the form of matrices whose dimensions are linked together (in each direction, the dimension and the spacing of the first studs are multiples of the repetition step of the second studs), guarantees furthermore, a contact surface between the first pad and the group of associated second pads, as long as the misalignment between the chips is included in a range of misalignment called tolerance interval or window. This constant contact surface makes it possible to obtain identical electrical performance whatever the value of the misalignment (within the tolerance range) and a homogeneous bonding energy, within the same plate or between several plates / chips. The quality of the bonding - and therefore the reliability of the stack - is therefore improved. Depending on the misalignment between the chips, the contact surface between the first pad and the group of second pads can extend to the entire surface of a second pad in the group or can be distributed over several (up to N) second pads of the group.
    In a preferred embodiment of the invention, the first dimension of the first interconnection pads is equal to the third repetition step, the second dimension of the first interconnection pads is equal to the fourth repetition step, the first distance is equal at the third repetition step and the second distance is equal to the fourth repetition step.
    In an alternative embodiment, the first dimension of the first interconnection pads is equal to twice the third repetition step, the second dimension of the first interconnection pads is equal to twice the fourth repetition step, the first distance is twice the third repetition step and the second distance is twice the fourth repetition step. The stack according to the invention may also have one or more of the characteristics below, considered individually or in all technically possible combinations.
    Preferably, the first dimension of the first interconnection pads is also equal to the first repeating step divided by 2 and the second dimension of the first interconnection pads is also equal to the second repeating step divided by 2. The density of metal on the surface of the first chip is then equal to 25%. This configuration corresponds to a homogeneous distribution of the metal in each of the first and second directions.
    The first repetition step is advantageously equal to the second repetition step. The distribution of the metal on the surface of the first chip is then the same in the first and second directions.
    The second interconnection pads have for example a rectangular, round or octagonal section.
    Preferably, the second interconnection pads have a first dimension in the first direction equal to the third repetition step divided by 2 and a second dimension in the second direction equal to the fourth repetition step divided by 2. The density of metal on the surface of the second chip is then equal to 25%. This configuration corresponds to a homogeneous distribution of the metal in each of the first and second directions.
    The third repetition step is advantageously equal to the fourth repetition step. The distribution of the metal on the surface of the second chip is then the same in the first and second directions.
    According to one development, the second chip comprises a layer of active components and a plurality of metal interconnection levels connecting the active components, and at least one of the metal interconnection levels is used to interconnect the N second interconnection pads of each group .
    BRIEF DESCRIPTION OF THE FIGURES
    Other characteristics and advantages of the invention will emerge clearly from the description which is given below thereof, by way of indication and in no way limiting, with reference to the appended figures, among which:
    - Figure 1 shows a 3D circuit incorporating a first example of stacking electronic chips according to the prior art;
    - Figure 2 shows a 3D interconnection structure used in a second example of stacking electronic chips according to the prior art;
    - Figure 3 shows a 3D interconnection structure used in a third example of stacking electronic chips according to the prior art;
    - Figure 4 shows a 3D interconnection structure used in a stack of electronic chips according to a first embodiment of the invention;
    - Figures 5A and 5B illustrate the 3D interconnection structure of Figure 4 in situations of misalignment of different values;
    - Figure 6 shows a 3D interconnection structure used in a stack of electronic chips according to a second embodiment of the invention;
    - Figure 7 shows a 3D interconnection structure used in a stack of electronic chips according to a third embodiment of the invention; and
    - Figure 8 shows a 3D interconnection structure used in a stack of electronic chips according to a fourth embodiment of the invention.
    For the sake of clarity, identical or similar elements are identified by identical reference signs in all of the figures.
    DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT
    In the description which follows, the term “3D interconnection structure” is used to mean all the interconnection pads which make it possible to electrically connect two electronic chips stacked (vertically) one on the other. These interconnection pads are present on one face of each electronic chip, which can be the front face or the rear face. The front face of an electronic chip designates the face of a substrate, generally made of a semiconductor material such as silicon, on which active components are formed, for example transistors, then (if applicable) passive components and metallic interconnection levels. The rear face of the electronic chip is the face of the substrate opposite the front face.
    The two electronic chips are bonded together, preferably by a direct bonding technique (ie without introducing any intermediate compound - such as an adhesive, a wax or a low-melting alloy - at the bonding interface ), for example of the metal-metal type or of the metal-dielectric hybrid type. The bonding can be carried out according to different approaches: front face against front face, rear face against rear face or front face against rear face. The two faces which are bonded together are substantially flat, their topology generally not exceeding 15 nm. There is then no space between the chips after their bonding, unlike other assembly technologies (typically by microbeads or micro-pillars), which have a significant topology (of the order of a few μιτι) and require the introduction of a polymer between the chips.
    Figure 4 is a partial sectional view of a stack of electronic chips according to a first embodiment of the invention. This view is taken at a bonding interface between two electronic chips and schematically represents a first 3D interconnection structure 400 ensuring the electrical connection between the two electronic chips.
    The 3D interconnection structure 400 comprises a plurality of identical first interconnection pads 401a belonging to a first electronic chip and a plurality of identical second interconnection pads 401b belonging to a second electronic chip. The face of the first chip, on which the first interconnection pads 401a open, is glued to the face of the second chip showing the second interconnection pads 401b. The first interconnection pads 401a and the second interconnection pads 401b are preferably made of metal, for example copper or aluminum, and participate in the bonding of the first and second chips.
    The second interconnection pads 401b of the second chip, as well as the first interconnection pads 401a of the first chip, are spaced from each other by electrically insulating portions 402, for example made of silicon oxide. The bonding surface of each chip is therefore composed of metal interconnection pads surrounded by a dielectric material.
    The first interconnection pads 401 a of the first chip are distinct and arranged in rows and columns, in the form of a matrix or mesh. The columns of first pads 401a have a first repetition step Pxi in a first direction X of the section plane of FIG. 4. This first repetition step Pxi is equal to the distance which separates the centers of two pads 401 a belonging to a same row and two consecutive columns. In the same way, the lines of first pads 401a have a second repetition step Pyi in a second direction Y of the plane, perpendicular to the first direction X. This second repetition step Pyi is equal to the distance which separates the centers of two studs 401a belonging to the same column and to two consecutive rows. In other words, the first interconnection pads 401a are reproduced periodically on the surface of the first chip, in both directions X and Y.
    The second interconnection pads 401b of the second chip are also separate and arranged in rows and columns. The columns of second pads 401b repeat in the first direction X according to a third repetition step Px2, while the rows of second pads 401b repeat in the second direction Y according to a fourth repetition step Py2. The third and fourth repetition steps Px2-Py2 are defined in the same way as the first and second repetition steps Pxi-Pyi, with respect to the centers of the second pads 401 b.
    The number of rows and columns, and therefore of interconnection pads on the surface of each chip, depends on the interconnection density sought and on the surface of the bonding surfaces of the chips. In order not to unnecessarily burden Figure 4, only three columns and three rows of first pads 401a are shown and only six columns and six rows of second pads 401b are shown.
    As illustrated in FIG. 4, the first repetition step Pxi (no X repetition of the first pads 401 a) may be different from the second repetition step Pyi (no Y repetition of the first pads 401a) and the third step of Px2 repetition (no X repetition of the second pads 401b) may be different from the fourth Py2 repetition step (no Y repetition of the second pads 401b). The first pads 401a and the second pads 402b are then in the form of rectangular meshes.
    The first interconnection pads 401a have a section, in the plane of the bonding face, of rectangular shape. The dimensions of the first pads 401a in the first direction X and in the second direction Y are denoted respectively Axi and Ayi.
    The section of the second interconnection pads 401 b (in the plane of the bonding face) can be of any shape, for example rectangular (cf. FIG. 4), round or octagonal. The dimensions of the second studs 401 b in the first direction X and in the second direction Y are denoted respectively Ax2 and Ay2. The distance which separates in the direction X two second consecutive pads 401b belonging to the same line is denoted Dx2 and the distance which separates in the direction Y two second consecutive pads 401b belonging to the same column is denoted Dy2.
    In this first embodiment, the dimension Axi in X of the first pads 401a is equal to the third repeat step Px2 and the dimension Ayi in Y of the first pads 401a is equal to the fourth repeat step Py2. In addition, the distance Dxi which separates in the direction X two first consecutive pads 401a of the same line, that is to say the width of the insulating portion 402 separating two consecutive columns of first pads 401 a, is equal to the third repetition step Px2. Similarly, the distance Dyi which separates in the direction Y two first consecutive pads 401a of the same column, that is to say the width of the insulating portion 402 separating two consecutive lines of first pads 401a, is equal to fourth repeat step Py2.
    Although physically separated, the second interconnection pads 401b are interconnected by group of N, preferably by means of metal tracks 403 located in a plane parallel to the bonding face of the second chip. Each group of second interconnection pads 401 b is electrically connected to a single first interconnection pad 401 a. To make this electrical connection, at least one second pad 401b of each group is in direct contact with the first pad 401 a associated with the group. The number N of second studs 401 b in the groups varies according to the dimensions Axi-Ayi of the first studs 401a and the spacings Dxi-Dyi between the first studs 401a. As an example, in the embodiment of FIG. 4, each first pad 401a is connected to four second interconnected pads 401b (N = 4).
    Preferably, the second chip comprises several levels of metallic interconnections (belonging to a functional block or set of technological levels called “Back End Of Line” or BEOL) connecting active components (belonging to a functional block called “Front End Of Line "Or FEOL), for example transistors. At least one of the metal interconnection levels is advantageously used to interconnect the N second interconnection pads of each group. In other words, the metal tracks 403 connecting the second pads 401b are added to this level of metallic interconnections. Advantageously, the metal tracks 403 are added to the last two levels of metal interconnections (i.e. the most distant from the active components), the density of which is lower. These last two levels are usually used to make the chip's "Power Delivery Network" and the creation of additional metal tracks 403 does not affect the performance of this grid.
    A feature of the interconnection structure 400 is that the contact surface S between each first pad 401a and the N second pads 401b of the associated group is independent of the misalignment linked to the bonding of the first and second chips, as long as this misalignment does not exceed (in X and in Y) threshold values delimiting a tolerance interval (or window).
    The configuration shown in Figure 4 is that of perfect alignment between the two chips (zero misalignment in X and Y). Each first pad 401a is centered on the group of second pads 401b to which it is connected. The contact surface S is distributed uniformly over the four second pads 401 b of the group. It is equal to the area of a second plot 401 b.
    FIGS. 5A and 5B show two other configurations of the interconnection structure 400 (after bonding of the chips), in which the misalignment between the chips is not zero. In the configuration of FIG. 5A, that of a moderate misalignment in X and in Y, the contact surface S is always distributed over the four pads of the group, but no longer uniformly. However, the contact surface S is nevertheless identical to the configuration of FIG. 4, because the sum of the contact surfaces of first pad 401a to second pad 401b (so-called individual contact surfaces) is equal to the area of a second pad 401b. In the configuration of FIG. 5B, that of an extreme misalignment in X and in Y (at the limit of the tolerance intervals), the contact between the first pad 401a and the group of second pads 401 b is only limited to a single second stud 401 b, over its entire surface. The contact surface S is therefore always the same.
    This constant contact surface, whatever the value of the misalignment (within the tolerance interval) between the two chips, makes it possible to standardize the electrical performance of one 3D stack to another, in particular their electrical resistance. This applies regardless of the transfer technique used: chip chip, plate chip or plate to plate (the misalignment between the chips can vary from one place to another of the plates, in particular between the center and the edge of the plates).
    A constant contact surface also implies an identical bonding energy between the different stacks, which is particularly beneficial in the case of chip to plate and plate to plate transfer techniques since it is then necessary to cut the stacks. The reliability of 3D circuits from a mechanical point of view is therefore generally improved.
    Finally, it can be seen that the distribution of the metal on the surface of the second chip (second interconnection pads 401b) is much better in the interconnection structure 400 than that obtained (for the upper chip) in the interconnection structure of the prior art (cf. FIG. 2, interconnection pads 104a). This is due to the fact that each first pad 401a is associated in the interconnection structure 400 with a multitude (at least 4) of second pads 401b, instead of only one in the prior art. Thanks to this better distribution of the metal, the manufacture of the second chip (before bonding) is facilitated, in particular the step of planarizing its bonding face by chemical mechanical polishing.
    FIG. 6 schematically represents a second 3D interconnection structure 600 belonging to a stack of chips according to a second embodiment of the invention.
    The second interconnection structure 600 represents a particular case of the first interconnection structure 400, since the first and second interconnection pads 401a-401b have a section of square shape. Consequently, the dimension Axi in X of the first pads 401a is equal to the dimension Ayi in Y of the first pads 401a and the dimension Axi in X of the second pads 401 b is equal to the dimension Ayi in Y of the second pads 401 b.
    As in the structure 400 of FIG. 4, the dimension Axi in X of the first pads 401 a is advantageously equal to the first repetition step Pxi divided by two and the dimension Ayi in Y of the first pads 401 a is advantageously equal to the second step of Pyi repetition halved. The density of metal di of the first chip, which represents the surface of the first pads 401 a on the total bonding surface, is then equal to 25%:
    A X1 XA Y1
    P X1 XP Y1
    P X1 XP Y1
    0.25
    A metal density di of 25% represents an optimal solution to facilitate the preparation of the first chip, and more particularly the mechanochemical polishing step of its bonding face, because the metal portions (pads 401a) in X and in Y are of the same width as the dielectric portions (402).
    It follows from these geometric considerations that the first repetition step Pxi is equal to the second repetition step Pyi (the mesh of first studs 401 a is therefore itself square). The distribution of the metal is then the same in the direction of the lines (X) and in the direction of the columns (Y).
    Similarly, the dimension Ax2 in X of the second pads 401b and the dimension Ay2 in Y of the second pads 401b are equal respectively to the third repetition step Px2 divided by two and to the fourth repetition step Py2 divided by two. The density of metal d2 on the surface of the second chip is then also equal to 25%:
    di = A X2 x A y2 = Ρχζ / 2 x Pr 72 = 0 25 X2 X Y2 X2 X Ργ2
    The manufacturing advantages described for the first chip are therefore also valid for the second chip. For comparison, the metal density of one of the two chips (the upper chip) in the interconnection structure of the prior art (see Fig. 2) is only about 6%.
    Because of these geometric choices, the third repetition step Px2 is equal to the fourth repetition step Py2 (the mesh of second interconnection pads 401b is therefore also square).
    The maximum misalignment authorized in X, noted below Fx, in the interconnection structure 600 is equal to half the dimension Ax2 of the second pads 401 b plus the distance Dx2 between two second consecutive pads 401 b. Indeed, a first pad 401 a must not come into contact with the second pads 401 b of the adjacent groups. The maximum misalignment authorized in X is therefore here equal to 3 Λ of the third repetition step Px2 (because Ax2 = Dx2 = Px2 / 2) or even 3/8 of the first repetition step Pxi (because Pxi = Axi + Dxi = 2 * Px2):
    / Λ γη 3 3
    F x = + (—— + D X2 = ± ~ Ρχ2 - = ±% Ρχΐ
    The tolerance window, represented by the zone 601 in FIG. 6, therefore has a length in X equal to 75% of the first repetition step Pxi.
    The maximum misalignment authorized in Y (denoted Fy) is identical to that authorized in X (because the distances, dimensions and no repetition in Y are the same as in X), i.e. a width tolerance window in Y equal to 75 % of the first repetition step Pxi.
    For comparison, in the interconnection structure of the prior art (Fig. 2), the tolerance window is only 50% of the repetition step (2 * 0.9 μιτι / 3.6 μιτι = 0.5), in X and in Y.
    For the same (first) repetition step (that is to say the same “functional” 3D interconnection density), the interconnection structure 600 according to the invention therefore tolerates a greater misalignment than the structure of interconnection of the prior art.
    FIG. 7 schematically represents a third 3D interconnection structure 700 belonging to a stack of chips according to a third embodiment of the invention.
    The third interconnection structure 700 differs from the second interconnection structure 600 only in the form of the second interconnection pads 401 b. The section of the second studs 401 b is indeed not limited to a rectangular (Fig. 4) or square (Fig. 6) shape. A constant contact surface S (whatever the misalignment in the tolerance interval) is indeed obtained even if the section of the second studs 401 b is not symmetrical in X and in Y. In the embodiment of the Figure 7, the contact surface S is still equal to the area of a second pad 401b.
    In a fourth interconnection structure 800 represented by FIG. 8, the first and second studs 401 a-401 b are of square section and organized according to also square meshes. The first repeat step Pxi is therefore equal to the second repeat step Pyi and the third repeat step Px2 is equal to the fourth repeat step Py2. The dimensions Axi (in X) and Ayi (in Y) of the first pads 401a, as well as the distances Dxi (in X) and Dyi (in Y) which separate the first pads 401a, are also equal to twice the third ( or fourth) no Px2 repetition (= Py2). The dimensions Ax2 (in X) and Ay2 (in Y) of the second pads 401b are equal to the third repetition step Px2 divided by 2. The densities di and d2 of metal are therefore always equal to 25%. The number N of second interconnected pads in each group is equal to 16 (they are distributed according to a 4x4 matrix). The contact area S is constant and equal to the area of four second studs 401b, regardless of the value of the misalignment within the tolerance range.
    The maximum misalignments authorized in X (Fx) and in Y (Fy) are equal to once the third repetition step Px2 plus half the distance Dx2 between two second consecutive pads 401b, i.e. here 5/4 of the third repetition step Px2 or even 5/16 of the first repetition step Pxi (because Pxi = Axi + Dxi = 4 * Px2):
    fDvo 5 5
    F X = F Y = + ly + P X2 = ± ^ Ρχ2 == + ^ Ρχΐ
    The tolerance window, represented by the area 801 in FIG. 8, therefore has a length in X and a width in Y equal to 62.5% of the first repetition step Pxi. The tolerance window of the fourth interconnection structure 800 is therefore less extensive than that of the second interconnection structure 600 (Fx = Fy = 75%) but always more extended than the tolerance window of the interconnection structure according to prior art.
    More generally, a constant contact surface S can be obtained with an interconnection structure of the type of FIG. 4 as long as it meets the following criteria:
    the dimension Axi in X of the first pads 401a is equal to m times the third repetition step Px2, where m is a first non-zero natural integer;
    - the dimension Ayi in Y of the first pads 401a is equal to n times the fourth repetition step Py2, where n is a second non-zero natural integer;
    - the distance Dxi which separates in the direction X two first consecutive pads 401a (of the same line) is equal to g times the third repetition step Px2, where g is a third non-zero natural integer;
    - the distance Dyi which separates in the direction Y two first consecutive pads 401a is equal to r times the fourth repetition step Py2, where r is a fourth non-zero natural integer.
    The natural numbers m, n, g and r can be equal or different from each other.
    The number N of second interconnection pads 401 b interconnected in each group then satisfies the following equation:
    N = (m + g) (n + r)
    The contact surface S between each first pad 401 a and the N second pads 401 b of the associated group is given by the following formula:
    S = 4x ^ + 2 x ( m -i) ^ + 2x (nl) (^) + (m - l) (n - 1) x S plot = mxnx S plot with S p t ot the area of a second interconnection pad 401 b.
    In the first embodiment (Fig. 4), the second embodiment (Fig. 6) and the third embodiment (Fig. 7), the natural numbers m, n, g and / are all equal to 1 (Axi = Px2, Ayi = Py2, Dxi = Px2 and Dyi = Py2). As indicated above, the number N of second pads 401b in each group is then equal to 4 (N = 4) and the contact area S is equal to the area S piot of a second interconnection pad 401 b (S = Spiot).
    In the fourth embodiment (Fig. 8), the natural integers m, n, g and r are all 2 (Axi = 2 * Px2, Ayi = 2 * Py2, Dxi = 2 * Px2 and Dyi = 2 * Py2) . The number N of second studs 401b in each group is then equal to 16 (N = 16), the contact surface S is equal to the area of four second studs 401b (S = 4 * S P iot).
    The interconnection structures 400, 600, 700 and 800 described below tolerate, in addition to a misalignment linked to the bonding of the chips (and represented by FIGS. 5A-5B), a shift of the interconnection pads within a chip. In other words, the contact surface S between a first pad 401 a and a group of second pads 401 b remains constant even if the distance between the pads 401 a or 401 b varies slightly within the matrix. This offset is variable depending on the position on the board (small between two neighboring studs, but can be significant between two distant studs on the board). It is for example due to an expansion of the materials or to misalignments during the steps of manufacturing the chips (photolithography steps in particular). The electrical performance of 3D interconnections, and in particular their electrical resistance, is therefore homogeneous within the same stack. For the same reason, the bonding energy is homogeneous within the same stack, which improves the mechanical strength and reliability of the stack.
    These interconnection structures can be used regardless of the value of the repetition step of the first pads 401a, called the "functional" repetition step because it fixes the density of the 3D interconnections in the stack. However, they prove to be particularly advantageous for a functional repetition step of less than 2 μm. Indeed, with such a repetition step, the 3D interconnection pads and the metal lines of the higher interconnection levels have very close dimensions. The advantage of having a constant contact surface S, and therefore a homogeneous electrical resistance, is therefore very strong. Conversely, when the functional repetition step is of the order of 4-5 μm or more, the 3D interconnection pads are larger and the resistance of the metallic lines is greater than that of the 3D interconnection pads. The variation of the contact surface S then influences to a lesser extent the overall electrical performance of the interconnections which connect the active components of the two chips (3D interconnections, metal lines of the interconnection levels and vias between the levels).
    Many variants and modifications of the stack of electronic chips according to the invention will appear to a person skilled in the art. The characteristics of the interconnection structures 400, 600, 700 and 800, described through FIGS. 4, 6 to 8, can be easily combined with one another. It is in particular possible to combine the characteristics relating to the shape of the second studs 401b, to the repeating steps in X and Y of the studs 401 a-401 b and to the dimensions of the studs 401 a-401 b relative to the repeating steps , to define new 3D interconnection structures enjoying the same advantages.
    The stack of electronic chips according to the invention comprises at least the first and second electronic chips. The first chip provided with the first interconnection pads 401a can be placed on the second chip provided with the second interconnection pads 401b, or vice versa. A stack of more than two electronic chips comprises more than one 3D interconnection structure and at least one of the electronic chips has interconnection pads on its two faces (front face and rear face).
    权利要求:
    Claims (9)
    [1" id="c-fr-0001]
    1. 3D stacking of electronic chips including:
    - A first chip having on a first face a plurality of first interconnection pads (401a) of rectangular section, arranged in rows and columns, the columns of first interconnection pads having a first repeating pitch (Pxi) in a first direction (X) and the lines of first interconnection pads having a second repeating pitch (Pyi) in a second direction (Y) perpendicular to the first direction;
    - A second chip having, on a second face glued to the first face of the first chip, a plurality of second interconnection pads (401b) arranged in rows and in columns, the columns of second interconnection pads having a third pitch repetition (Px2) in the first direction (X) and the lines of second interconnection pads having a fourth repetition pitch (Py2) in the second direction (Y), at least part of the second interconnection pads (401b ) being in contact with the first interconnection pads (401a) to electrically couple the first and second chips;
    characterized in that:
    - the first interconnection pads (401a) have a first dimension (Axi) in the first direction (X) equal to the third repetition step (Px2), where m is a non-zero natural integer, and a second dimension (Ayi ) in the second direction (Y) equal to n times the fourth repetition step (Py2), where n is a non-zero natural integer;
    - the first interconnection pads belonging to the same row and to two consecutive columns are separated in the first direction (X) by a first distance (Dxi) equal to g times the third repetition step (Px2), where q is a non-zero natural integer;
    - the first interconnection pads belonging to the same column and to two consecutive lines are separated in the second direction (Y) by a second distance (Dyi) equal to r times the fourth repetition step (Py2), where r is a non-zero natural integer;
    - the second interconnection pads (401b) are interconnected in a plurality of groups, each group comprising a number N of second interconnection pads (401b) interconnected such that:
    N = (m + q) (h + r), each group being electrically connected to a first interconnection pad (401a) by at least one of the second interconnection pads (401b) of the group.
    [2" id="c-fr-0002]
    2. Stack according to claim 1, in which the first dimension (Axi) of the first interconnection pads (401a) is also equal to the first repetition step (Pxi) divided by 2 and in which the second dimension (Ayi) of first interconnection pads is also equal to the second repetition step (Pyi) divided by 2.
    [3" id="c-fr-0003]
    3. Stack according to claim 2, in which the first repeating step (Pxi) is equal to the second repeating step (Pyi).
    [4" id="c-fr-0004]
    4. Stack according to any one of claims 1 to 3, wherein the second interconnection pads (401b) have a rectangular, round or octagonal section.
    [5" id="c-fr-0005]
    5. Stack according to any one of claims 1 to 4, in which the second interconnection pads (401b) have a first dimension (Ax2) in the first direction (X) equal to the third repetition step (Px2) divided by 2 and a second dimension (Ay2) in the second direction (Y) equal to the fourth repetition step (Py2) divided by 2.
    [6" id="c-fr-0006]
    6. Stack according to claim 5, in which the third repetition step (Px2) is equal to the fourth repetition step (Py2).
    [7" id="c-fr-0007]
    7. A stack according to any one of claims 1 to 6, in which:
    - the first dimension (Axi) of the first interconnection pads (401a) is equal to the third repetition step (Px2);
    - the second dimension (Ayi) of the first interconnection pads is equal to the fourth repetition step (Py2);
    - the first distance (Dxi) is equal to the third repetition step (Px2); and
    - the second distance (Dyi) is equal to the fourth repetition step (Py2).
    [8" id="c-fr-0008]
    8. A stack according to any one of claims 1 to 6, in which:
    - the first dimension (Axi) of the first interconnection pads (401a) is equal to twice the third repetition step (Px2);
    - the second dimension (Ayi) of the first interconnection pads is equal to twice the fourth repetition step (Py2);
    - the first distance (Dxi) is equal to twice the third repetition step (Px2); and
    - the second distance (Dyi) is equal to twice the fourth repetition step (PY2).
    [9" id="c-fr-0009]
    9. Stack according to any one of claims 1 to 8, in which the second chip comprises a layer of active components and a plurality of metal interconnection levels connecting the active components, and in which at least one of the interconnection levels metallic is used to interconnect the N second interconnection pads (401b) of each group.
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    同族专利:
    公开号 | 公开日
    FR3078823B1|2020-02-21|
    JP2019161228A|2019-09-19|
    US20190279965A1|2019-09-12|
    EP3540769B1|2020-12-09|
    EP3540769A1|2019-09-18|
    US10818639B2|2020-10-27|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    FR2828334A1|2001-08-03|2003-02-07|Schlumberger Systems & Service|Restoration of electrical and mechanical connectability to an electrical device with a face equipped with contact studs using an fixing layer crossed by conducting tracks|
    US20080156521A1|2006-12-27|2008-07-03|Kabushiki Kaisha Toshiba|Printed wiring board, printed circuit board, and electronic device|
    US20140252606A1|2011-10-17|2014-09-11|Panasonic Corporation|Integrated circuit, multicore processor apparatus, and method for manufacturing integrated circuit|
    US20150008575A1|2013-07-03|2015-01-08|Taiwan Semiconductor Manufacturing Company Ltd.|Semiconductor device and manufacturing method thereof|
    US9343419B2|2012-12-14|2016-05-17|Taiwan Semiconductor Manufacturing Company, Ltd.|Bump structures for semiconductor package|
    KR20170062616A|2015-11-27|2017-06-08|삼성전자주식회사|Semiconductor device|KR20200026576A|2018-09-03|2020-03-11|삼성전자주식회사|Semiconductor package|
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    法律状态:
    2019-03-29| PLFP| Fee payment|Year of fee payment: 2 |
    2019-09-13| PLSC| Search report ready|Effective date: 20190913 |
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1852110|2018-03-12|
    FR1852110A|FR3078823B1|2018-03-12|2018-03-12|3D STACK OF ELECTRONIC CHIPS|FR1852110A| FR3078823B1|2018-03-12|2018-03-12|3D STACK OF ELECTRONIC CHIPS|
    EP19161512.9A| EP3540769B1|2018-03-12|2019-03-08|3d stack of electronic chips|
    US16/298,414| US10818639B2|2018-03-12|2019-03-11|3D stack of electronic chips|
    JP2019043574A| JP2019161228A|2018-03-12|2019-03-11|Three-dimensional stack of electronic chips|
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